--test rundy 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity test_s0 is
    Port ( din : in  STD_LOGIC_VECTOR (7 downto 0);
		dout : out  STD_LOGIC_VECTOR (7 downto 0));
end test_s0;


architecture Behavioral of test_s0 is
component InSbox0 is
    Port ( i : in  STD_LOGIC_VECTOR (15 downto 0);
		o : out  STD_LOGIC_VECTOR (15 downto 0));
end component InSbox0;

component Sbox0 is
    Port ( i : in  STD_LOGIC_VECTOR (15 downto 0);
		o : out  STD_LOGIC_VECTOR (15 downto 0));
end component Sbox0; 

signal sdin, sis, iso : STD_LOGIC_VECTOR (15 downto 0);
begin
sdin(7 downto 0) <=  din(7 downto 0);
sdin(15 downto 8) <= X"AF";

s: Sbox0 port map (sdin, sis);
ins: InSbox0 port map (sis,iso);

dout(7 downto 0)<=iso(7 downto 0);
end Behavioral;
